- Hands on experience in all the Phases of Physical design and handling multi million ASIC/SoC and should have involved least 1to 3 SoC tapeouts. - Hands on experience Block level floor planning, pin placement, macro placement, multi -power domain complexities, CTS, balancing the clocks between multiple clocks. - Hands on experience on LVS, DRC cleaning up, timing closure, Electrical Rule fixes and antenna checks. - Hands on experience on Timing, EM, IR drop, signal integrity analysis..
4 Lac-5 Lac P.A
IT Software - Embedded VLSI
Permanent Job, Full time
- Hands on experience in Power planning, clock distribution, IP integration, SPEF extraction, DFM and Tapeout - Expertise in scripting languages like PERL,Shell etc Responsible for all aspects of physical design implementation from Netlist to GDSII.
UG - Bachelor of Engineering/Technology (BE/B.Tech) - Electronics & Communication
PG - PG Not Required - Any Specialization
Cerification - N/A
Exclusive opening for Design Engineer in Mumbai!!!